VLSI in South Dum Dum

South Dum Dum, Education & Learnings
 ₹  Please Contact

Mr N Bhattacharya

Contact details

+91 9830303108

Mr N Bhattacharya

Contact details

+91 9830303108

Description

EFY Tech Center Kolkata


VLSI/FPGA DESIGN
Objectives of the course

SCHEDULE OF PROGRAMMING EXERCISES USING FPGA BASYS2BOARD VERILOG LAB SESSIONS
VERILOG/VHDL CODES FOR THE FOLLOWING DIGITAL CIRCUITS:-
JK FLIP FLOP WITH ASYNCHRONOUS RESET.
AND T FLIPS FLOP.
BINARY COUNTER.
Up-Down Counter (Simple 8-bit Counter)
Divide by 2 Counter
Divide by 3 Counter
ALU.
TRAFFIC LIGHT SIGNAL.
HALF AND FULL ADDER.
MULTIPLEXOR (2:1, 4:1 USING 2:1, 8:1).
DEMULTIPLEXOR (1:8).
ENCODER WITH AND WITHOUT PRIORITY (8:3).
3:8 DECODERS.
2 BIT COMPARATOR.
LED Blinking
BINARY TO GRAY (USING EXOR GATES).

http://www.efytechcenterkolkata.com/

Contact Information
EFY Tech Center, Kolkata
PH: 033-40606333
Mr. N. Bhattacharya,Mob: 9830303108

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